hw_elab

Elaboration

It creates a hierarchical representation of the design by connecting modules and resolving dependencies between them.

Common elaboration errors:

1. System Verilog elaboration error involving an undeclared signal while instantiating a module
2. Suppose you have two Verilog modules, ModuleA and ModuleB, and you want to instantiate ModuleB within ModuleA. However, you accidentally misspell the module name when instantiating it

and many more...