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FPGA MAFIAFabric RISCV_Cores Cache IPs FPGA

TFM MAFIA_Build GitHub - Project GitHub - Wiki

Intro
Cheat Sheet
HAS
MAS
Verification

Verification
Random_and_stress

Random_and_stress

Dedicated Test Intro

Contributors

Amichai Ben-David
Noam Sabban
Shmuel Sfez
Yeonatan Perelman
Daniel Kaufman
Roman Gilgor

RTL Units

Fabric
- Tile
- Router
RISCV Cores
Memory Subsystem
- Instruction Cache
- Data Cache
- Memory Controller

TFM

Project Tool
- Git & GitHub
- RISCV GCC
- Modelsim
- Quartus
System-Verilog

GitHub - links

GitHub - FPGA MAFIA
GitHub - FPGA MAFIA WIKI

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